1. Field of the Invention
The present invention relates to integrated circuit implementations of high-speed amplifiers, and more specifically to a preferred implementation of a gain-setting resistor in a high-speed amplifier integrated circuit.
2. Description of the Related Art
FIG. 1 is a schematic diagram of a high-speed cascode amplifier for driving a cathode ray tube (CRT) of a display device (e.g., an HDTV CRT). The amplifier has an input buffer stage, a cascode gain stage, and a cascode Darlington push-pull output stage biased at Class B for driving the cathode of a CRT. The circuit asserts amplified output potential Vout at an output node in response to input potential Vin, when biased by bias potential Vb (when supply voltage Vccxe2x88x92Vee is applied across its top and bottom rail). The FIG. 1 amplifier includes cathode current detection circuitry (including PNP transistors X10 and X12 and resistors R12 and R13, connected as shown) from which an output signal (Iout) indicative of the cathode current can be drawn (by circuitry not shown in FIG. 1) from node T of FIG. 1.
The FIG. 1 amplifier is typically implemented as an integrated circuit (or portion of an integrated circuit), with some or all of its resistors comprising layers of polysilicon over a layer of field oxide (with a substrate of P-type semiconductor material under the field oxide layer). Such an integrated circuit implementation will be assumed in the following description.
In FIG. 1, resistors RC1 and RC2 are connected in series between nodes X and Y. Node X is coupled to the top rail, which is at potential Vcc. Node Y is coupled to the base of transistor X7, to the collector of transistor X4, and to one end of resistor R8.
Supply voltage (Vccxe2x88x92Vee) is typically a high voltage (e.g., 145 volts), and input potential Vin typically varies rapidly during operation.
In typical integrated circuit implementations of the FIG. 1 amplifier, each of resistors RC1 and RC2 comprises a polysilicon strip (or multiple polysilicon strips connected in series) over a layer of field oxide, with a substrate of P-type semiconductor material under the field oxide layer. FIG. 2 is a diagram of one such implementation of portion 2 (including resistors RC1 and RC2) of FIG. 1. As shown in FIG. 2, resistor RC1 comprises polysilicon strips RS1 and RS2 and metal connector M2 which connects strip RS1 with strip RS2. Resistor RC2 comprises polysilicon strips RS3 and RS4 and metal connector M4 which connects strip RS3 with strip RS4. Metal contact M1 (which is node X of FIG. 1) is coupled between one end of resistor RC1 and the top rail of FIG. 1. Metal connector M3 connects the other end of resistor RC1 with one end of resistor RC2. Metal contact M5 (which is node Y of FIG. 1) is coupled between the other end of resistor RC2 and the base of transistor X7 (shown in FIG. 1).
A field oxide layer (not shown in FIG. 2, to allow substrate 3 to be shown) is deposited on the exposed upper surface of substrate 3. The four parallel strips RS1, RS2, RS3, and RS4 of polysilicon are deposited on the oxide layer, and metal connectors M2, M3, and M4 (and metal contacts M1 and M5) are deposited on the indicated portions of strips RS1-RS4 and the oxide layer.
A limitation of the above-described implementation of resistor RC2 (as a polysilicon resistor having the structure described with reference to FIG. 2) is that the stray capacitance of such polysilicon resistor (over the field oxide on which it is formed) slows down the output transient response of the FIG. 1 amplifier. Thus, the absolute value of the amplifier""s gain is necessarily reduced in order to achieve faster transient response (by implementing resistor RC2 with reduced resistance).
U.S. Pat. No. 5,977,610, issued on Nov. 2, 1999 (and assigned to the assignee of the present invention), discloses polysilicon resistor structures other than the structure described with reference to FIGS. 1 and 2. U.S. Pat. No. 5,977,610 describes several ways to form a polysilicon resistor over one tub or multiple tubs of N-type semiconductor material in a substrate of P-type semiconductor material.
FIG. 3 is a schematic diagram of a high-speed cascode amplifier which differs from the FIG. 1 amplifier only in that resistor RC2 is implemented as a polysilicon resistor of one of the types disclosed in U.S. Pat. No. 5,977,610, in order to reduce its stray capacitance over the field oxide on which it is formed, and thus to improve the amplifier""s output transient response without reducing the absolute value of its gain. Portion 12 of the FIG. 3 circuit (including resistor RC2, a diode that underlies RC2, and resistor RC1) is implemented as shown in FIG. 4.
As shown in FIG. 4, resistor RC1 is implemented in the same way as in FIG. 2 and the description of its structure will not be repeated with reference to FIG. 4. In FIG. 4, resistor RC2 comprises polysilicon strips RS3 and RS4 and metal connector M4 connecting strip RS3 with strip RS4. Metal connector M3 connects one end of resistor RC2 with one end of resistor RC1. Metal contact M5 (which is node Y of FIG. 3) is coupled between the other end of resistor RC2 and the base of transistor X7 (shown in FIG. 3).
Resistor RC2 of FIG. 4 (and the amplifier of FIG. 3 including it) is manufactured on substrate 3 of P-type semiconductor material. At the location on substrate 3 where resistor RC2 is to be formed, a diode is implemented by forming a layer of N-type semiconductor material 4 on substrate 3 (such as by implanting N-type impurities in a rectangular region of the substrate material and then removing unwanted portions of the N-type semiconductor material). After the initial formation step, layer 4 has uniform (relatively small) thickness, except that it has relatively large thickness at one portion under which metal contact M6 is to be formed (so that layer 4 extends all the way up to contact M6).
After the initial step in forming N-type layer 4 on P-type substrate 3, layer 4 is enlarged by growing an epitaxial layer of N-type semiconductor material over the initially formed N-type material (except for the thick portion of the N-type material on which contact M6 is to be formed) and over a portion of P-type substrate 3 surrounding the outer periphery of the initially formed N-type material. FIG. 4 shows P-type semiconductor substrate material 3 surrounding the outer periphery of completely formed N-type semiconductor layer 4. Completely formed N-type semiconductor layer 4 comprises a large, single tub (well) of N-type semiconductor material in P-type substrate 3.
A field oxide layer is deposited on the exposed upper surfaces of substrate 3 and completely formed tub 4 of circuit portion 12, but not over the portion of tub 4 on which contact M6 is to be formed. The field oxide layer is not shown in FIG. 4 to allow depiction of substrate 3 and tub 4. After deposition of the field oxide layer, parallel polysilicon strips RS1, RS2, RS3, and RS4 are deposited on the field oxide layer. Finally, a pattern of metal (having high electrical conductivity) is deposited on portions of the polysilicon material, on portions of the field oxide layer between the polysilicon strips, and on the bare portion of tub 4, to implement metal contacts and connectors M1, M2, M3, M4, M5, and M6. Thus, the completed resistor RC2 comprises strip RS3 (connected at one end to connector M3 and at the other end to connector M4) and strip RS4 (connected at one end to connector M4 and at the other end to contact M5), overlying tub 4 of N-type semiconductor material. Metal contact M1 of resistor RC1 is coupled to node X (of FIG. 3) so that current can flow from contact M1 through resistor RC1 and connector M3 to one end of polysilicon resistor RC2, and then through strip RS3, connector M4, and strip RS4, to the contact M5 at the opposite end of resistor RC2.
Metal contact M6 is deposited on tub 4 at node Z of FIG. 3. To xe2x80x9cbootstrapxe2x80x9d tub 4 of FIG. 4 (and thus the FIG. 4 implementation of resistor RC2) to FIG. 3""s output node, metal contact M6 (and thus tub 4) is coupled to FIG. 3""s output node (which is at the potential Vout). Such bootstrapping reduces the effect of resistor RC2""s stray capacitance over the underlying field oxide layer, causing the leading and trailing edges of the FIG. 3 amplifier""s response to time-varying input potential Vin (e.g., a square wave potential Vin) to have shorter rise and fall times than would the FIG. 1 amplifier""s response to the same input potential. This is apparent, for example, from FIGS. 7 and 8 which show the response of the FIG. 1 amplifier (and the FIG. 3 amplifier) to a square wave potential Vin, when such amplifier is connected as is amplifier 20 of FIG. 9.
FIG. 9 is a schematic diagram of a circuit for testing a cathode driver amplifier 20, which can be any of the amplifiers of FIG. 1, 3, and 5. The output node of amplifier 20 is coupled through resistor R1 to the cathode of CRT display device 21, the input node of amplifier 20 is coupled through resistor R2 to voltage source 22, voltage source 23 holds amplifier 20""s top rail at Vcc volts above ground, and voltage source 24 provides bias potential Vb to amplifier 20. Node T of the amplifier is coupled to sense resistor Rs, so that current Iout flows from Node T to ground through the sense resistor Rs.
FIGS. 7 and 8 indicate the result of operating the FIG. 9 circuitry with amplifier 20 implemented as the circuit of each of FIGS. 1, 3, and 5. Curve 31 of FIG. 7 is a graph of the output potential (Vout) of the FIG. 3 circuit as a function of time, in response to a square wave input potential Vin (having period 300 nsec), with Vccxe2x88x92Vee=145 volts, Vbxe2x88x92Vee=8 volts, and Vinxe2x88x92Vee varying between 2 volts and 0 volts. Curve 30 of FIG. 7 is a graph of the output potential (Vout) of the FIG. 1 circuit as a function of time, under the same conditions and in response to the same square wave input potential Vin. Curve 32 of FIG. 7 is a graph of the output potential (Vout) of the FIG. 5 circuit (to be described below) as a function of time, under the same conditions and in response to the same square wave input potential Vin. FIG. 8 is an enlarged detail of a portion of each of the three curves of FIG. 7.
As is apparent from FIGS. 7 and 8, the leading and trailing edges of curve 31 desirably have shorter rise and fall times than do the corresponding edges of curve 30. In general, the leading and trailing edges of the FIG. 3 amplifier""s response to time-varying input potential Vin have shorter rise and fall times than do the FIG. 1 amplifier""s response to the same input potential.
However, the FIG. 4 implementation of resistor RC2 is inferior in one respect to the FIG. 2 implementation of resistor RC2. This is due to the fact that since resistor RC2 (in the FIG. 4 implementation) is formed over a large N-tub-to-P-substrate diode, there is typically a leakage resistance (labeled as xe2x80x9cR_Leakxe2x80x9d in FIG. 3) between contact M6 and substrate 3 through which a significant leakage current can flow, especially when the output potential Vout is much greater than the bottom rail potential Vee (e.g., when Vout is close to Vcc, and Vccxe2x88x92Vee=145 volts).
FIG. 10 is a graph of the DC response of the FIG. 1 circuit (at each of and the output node) measured while operating the FIG. 9 circuitry with amplifier 20 implemented as in FIG. 1 (and resistor RC2 as in FIG. 2). Specifically, curve 34 of FIG. 10 is the current flowing from FIG. 1""s output node (at the output potential Vout) through resistor R1 of FIG. 9, as Vin slowly rises to Vee+1.95 volts from Vee volts (with Vccxe2x88x92Vee=145 volts, and Vbxe2x88x92Vee=8 volts). Curve 35 of FIG. 10 is the current Iout flowing from node T of FIG. 1 through resistor Rs of FIG. 9, as Vin slowly rises to Vee+1.95 volts from Vee volts (with Vccxe2x88x92Vee=145 volts, and Vbxe2x88x92Vee=8 volts).
FIG. 11 is a graph of the DC response of the FIG. 3 circuit (at each of node T and the output node) measured while operating the FIG. 9 circuitry with amplifier 20 implemented as in FIG. 3 (and resistor RC2 as in FIG. 4). Curve 44 of FIG. 11 is the current flowing from FIG. 3""s output node (at the output potential Vout) through resistor R1 of FIG. 9, as Vin slowly rises to Vee+1.95 volts from Vee volts (with Vccxe2x88x92Vee=145 volts, and Vbxe2x88x92Vee=8 volts). Curve 45 of FIG. 11 is the current Iout that flows from node T of FIG. 3 through resistor Rs of FIG. 9, in response to the same slow rise of Vin.
FIG. 10 shows that the ratio of the cathode current flowing from FIG. 1""s output node (through resistor R1) to the current Lout flowing from node T of FIG. 1 (through resistor Rs) remains nearly constant for all values of input potential Vin. However, FIG. 11 shows that the ratio of the cathode current flowing from FIG. 3""s output node (through resistor R1) to the current lout flowing from node T of FIG. 3 (through resistor Rs) depends on the value of input potential Vin, with the ratio being significantly greater for large values than for small values of potential Vin. Thus, the current lout drawn from node T of FIG. 3 is not accurately indicative of the cathode current flowing from FIG. 3""s output node (through resistor R1) to the CRT display device, whereas the current lout drawn from node T of FIG. 1 is accurately indicative of the cathode current flowing from FIG. 1""s output node to the CRT display device. The error inherent in the FIG. 3 circuit""s ability to indicate the cathode current flowing from its output node to a CRT display device results from leakage of some of the cathode current through the above-discussed leakage resistance R_Leak.
Until the present invention, was not known how to implement a gainsetting resistor in an amplifier of the type shown in FIGS. 1 and 3 to allow the amplifier to respond rapidly to rapid variations in its input signal (as can the FIG. 4 implementation of resistor RC2) while also allowing accurate detection of the cathode current drawn from the amplifier""s output node by measuring a current (other than the cathode current) drawn from a node (other than the amplilier""s output node ) as can the FIG. 2 implementation of resistor RC2xe2x80x2.
In a class of embodiments, the invention is an integrated circuit including a resistor (preferably a strip of polysilicon, or multiple, series connected pofysilicon segments) that overlies (at least partially) a first tub of semiconductor material of a first polarity (i.e., N-type or P-type material), where the first tub is formed in a second tub of semiconductor material having the opposite polarity, and the second tub of semiconductor material is formed in a semiconductor substrate having the first polarity. The second tub forms the base of a vertical bipolar transistor, the first tub forms the emitter of the transistor, and the substrate forms the collector of such transistor. In one embodiment, the transistor is a vertical PNP transistor, the first tub is the transistor""s emitter and consists of P-type semiconductor material, the second tub is the transistor""s base, and the substrate is the transistor""s collector. In preferred embodiments, the integrated circuit is an amplifier and the resistor is a gain-setting resistor.
In typical embodiments, the resistor of the inventive integrated circuit extends between a first node (whose potential typically varies in response to changes in an input signal) and a second node (whose potential varies in response to changes in the input signal), and the first tub is bootstrapped in the sense that it is coupled to a third node of the integrated circuit whose potential changes (in response to a change in the input signal) in such a direction as to pull the potential at the second node in a desired direction. In preferred embodiments, the resistor extends between a first node of the integrated circuit and a second node (whose potential varies in response to changes in the input signal), and the resistor is implemented with double bootstrapping in the sense that the first tub is coupled to a third node of the integrated circuit whose potential changes (in response to a change in the input signal) in such a direction as to pull the potential at the second node in a desired direction and the second tub is coupled to a fourth node of the integrated circuit whose potential also changes (in response to a change in the input signal) in such a direction as to pull the potential at the second node in a desired direction, without significant current leakage from the first tub to the substrate. For example, the third node can be the output node of a high-speed cascode amplifier, and the fourth node can be the base of a bipolar transistor of a cascode Darlington push-pull output stage of such high-speed cascode amplifier).
In a class of preferred embodiments, the invention is a high-speed cascode amplifier (for example, of the type shown in FIG. 5), the gain-setting resistor is coupled to a second resistor, and the second resistor is coupled to the top rail. The top rail potential is fixed, and bootstrapping is implemented by coupling the first tub to the amplifier""s output node. Preferably also, the second tub is coupled to another node of the amplifier (e.g., to the base of a bipolar transistor of a cascode Darlington push-pull output stage of the amplifier).